Senior Design Verification Engineer

Job Title: Principal Software Engineer – VIP (Verification IP)
Location: Noida
Experience: 7-10 yrs
Job Summary
We are looking for a Principal Engineer for our Verification IP (VIP) team to design and develop high-quality VIP solutions for next-generation high-speed protocols. The role involves working on architecture, development, and validation of protocol-compliant VIPs.
Key Responsibilities
Architect, design, and develop Verification IP (VIP) for industry-standard protocols.
Lead development of VIP using SystemVerilog/UVM methodologies
Define verification strategies, test plans, and coverage models
Drive protocol compliance, debugging, and performance optimization
Mentor junior engineers and provide technical leadership
Work on customer issues, feature enhancements, and next-gen protocol adoption
Required Skills & Experience
Strong expertise in SystemVerilog and UVM-based verification
Proven experience in VIP development / protocol verification
Deep understanding of one or more protocols:
PCIe , Ethernet, CXL, UCIe, UALink
Strong debugging skills at protocol and transaction level
Experience with coverage-driven verification, assertions (SVA), and scoreboarding
Familiarity with simulation tools (Xcelium/VCS/Questa)
Preferred Qualifications
Exposure to AI/ML-driven verification or Python-based automation
Experience in performance analysis and system-level validation
Knowledge of Formal Verification concepts is a plus
Prior experience in customer-facing or product engineering roles
Why Join Us
Work on cutting-edge high-speed protocols and next-gen standards
Opportunity to contribute to industry-leading VIP products
Collaborative environment with global semiconductor leaders
Strong career growth into technical leadership and architecture roles