Senior Principal RTL design Engineer

About the Company

Cadence is looking for RTL design engineers with 6-11 years of experience for positions in Bangalore, Hyderabad, Noida.

About the Role

We seek candidates to lead the LPDDR6/5X DDR Controller for Mobile Application Micro-architecture and make significant contributions to the RTL Design Effort.

Responsibilities

Owning the majority of RTL efforts towards the LPDDR6/5X DDR Controller
Focusing on optimal PPA (Performance, Timing, and Area)
Involving design architecture and RTL changes from scratch for all new features according to JEDEC specifications for the LPDDR6/5X DDR Controller

Qualifications

M.Tech/B.Tech in VLSI or ECE.

Required Skills

Interested candidates are encouraged to share their updated profiles to dsupriya@cadence.com.