Silicon Physical Design Engineer, Google Cloud

MINIMUM QUALIFICATIONS:

* Bachelor's degree in Electrical Engineering, Computer Engineering, Computer
Science, or a related field, or equivalent practical experience.

* 4 years of experience with physical design.
* Experience with System on a Chip (SoC) cycles.

PREFERRED QUALIFICATIONS:

* Master's degree or PhD in Electrical Engineering, Computer Engineering or
Computer Science, with an emphasis on computer architecture.

* Experience in coding with System Verilog and scripting with TCL.
* Experience with multiple cycles of SoC in ASIC design.

* Experience with layout verification and design rules.
* Experience in VLSI design in SoC.

ABOUT THE JOB:

Be part of a team that pushes boundaries, developing custom silicon solutions
that power the future of Google's direct-to-consumer products. You'll contribute
to the innovation behind products loved by millions worldwide. Your expertise
will shape the next generation of hardware experiences, delivering unparalleled
performance, efficiency, and integration.
The AI and Infrastructure team is redefining what’s possible. We empower Google
customers with breakthrough capabilities and insights by delivering AI and
Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our
customers include Googlers, Google Cloud customers, and billions of Google users
worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering
the development of our cutting-edge AI models, delivering unparalleled computing
power to global services, and providing the essential platforms that enable
developers to build the future. From software to hardware our teams are shaping
the future of world-leading hyperscale computing, with key teams working on the
development of our TPUs, Vertex AI for Google Cloud, Google Global Networking,
Data Center operations, systems research, and much more.

RESPONSIBILITIES:

* Take ownership of one or more physical design partitions or top level.
* Drive to the closure of timing and power consumption of the design.
* Contribute to design methodology, libraries, and code review.
* Define the physical design related rule sets for the functional design
engineers.