Sr. Manager 2

About Us

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs.

Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolve’s design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead in the cycle, thus reducing expensive re-design costs, and risks. We actively invest in the R&D center of excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics, Automotive, Industrial and Medical segments. Tessolve’s Embedded Engineering services enable customers a faster time-to-market through deep domain expertise, innovative ideas, diverse embedded hardware & software services, and built-in infrastructure with world-class lab facilities.

Tessolve’s clientele includes Tier 1 clients across multiple market segments, 9 of the top 10 semiconductor companies, start-ups, and government entities. We have a global presence over 12 countries with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose.

For more details, visit https://www.tessolve.com/

Job Overview**

This Design Verification Engineer role focuses on IP and protocol verification within semiconductor/VLSI projects in Bangalore/Hyderabad/India. The role involves developing UVM/SystemVerilog verification environments, verifying high-speed interfaces and IPs, driving coverage closure, debugging RTL and gate-level issues, and collaborating across design, architecture, and validation teams to ensure reliable IP and subsystem delivery. The position adds value by improving verification quality, accelerating time-to-silicon, and enabling robust protocol-compliant IP releases.

Job Designation**: Design Verification Engineer – IP Verification
Years of Exp**: 5–8 Years / 10–15 Years
Job Location**: Bangalore / Hyderabad / India
What you'll do**
Develop and execute verification plans for complex IPs and SoCs
Build UVM/SystemVerilog-based test environments for high-speed interfaces
Verify protocols such as PCIe, USB, DDR, Ethernet, AXI, AHB, APB, MIPI, SATA, SerDes
Create reusable testbenches, components, scoreboards, checkers, and assertions
Drive functional, code, and assertion coverage closure across projects
Debug RTL and gate-level simulation issues and provide actionable fixes
Collaborate with design, architecture, and validation teams for feature verification
Manage regression suites, test planning, and verification signoff activities
Contribute to IP and subsystem verification methodologies and reuse strategies
Who you are**
Proficient with SystemVerilog, UVM, and Verilog for verification development
Experienced in high-speed protocol verification and assertion-based techniques
Skilled with simulators like VCS, QuestaSim, or Xcelium for simulation and debugging
Comfortable scripting with Python, Perl, or Shell to automate verification tasks
Strong at debugging, root-cause analysis, and problem resolution
Familiar with coverage-driven verification methodologies and metrics
Collaborative communicator who works effectively with cross-functional teams
Job Overview**

This SoC Verification Engineer role targets end-to-end SoC and subsystem verification for semiconductor projects in Bangalore/Hyderabad. Responsibilities include defining SoC verification strategies, building UVM/SystemVerilog testbenches, validating integrations of processors, interconnects, and memory subsystems, and supporting regression, power-aware, and performance verification to ensure silicon readiness and system reliability.

Job Designation**: SoC Verification Engineer
Years of Exp**: 8–12 Years
Job Location**: Bangalore / Hyderabad
What you'll do**
Define and execute SoC-level verification strategies and detailed verification plans
Build and maintain UVM/SystemVerilog testbenches for SoC and subsystem verification
Verify integration of IPs, processors, interconnects, memory subsystems, and peripherals
Perform functional, performance, and power-aware verification and regression management
Develop reusable VIPs, monitors, scoreboards, assertions, and coverage models
Debug RTL, gate-level, and system-level integration issues for silicon readiness
Drive coverage closure across functional, code, and assertion domains
Support silicon bring-up and post-silicon validation when needed
Who you are**
Strong in SystemVerilog, UVM, and Verilog for SoC verification workflows
Experienced in SoC/subsystem verification and AMBA/protocol-based integrations
Knowledgeable in assertion-based verification and coverage-driven methodologies
Skilled with simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa
Proficient scripting skills in Python, Perl, or Shell for automation needs
Strong debugging, problem-solving, and cross-functional collaboration abilities
Familiarity with low-power verification, formal methods, emulation, or firmware interaction is a plus

Tessolve Semiconductor Private Limited, as well as its affiliates and subsidiaries (“Tessolve”) does not require job applicants to make any payments at any stage of the hiring process. Any request for payment in exchange for a job opportunity at Tessolve is fraudulent and should be ignored. If you receive any such communication, we strongly advise you to refrain from making any payments and to promptly report the incident to us at hr@tessolve.com. Tessolve is not responsible for any losses incurred due to such fraudulent activities